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Senior Formal Verification Engineer - Vector Unit at TechBiz Global GmbH

Posizione Senior Formal Verification Engineer - Vector Unit
Pubblicato 08 Jul 2026
Scaduto 07 Aug 2026
Azienda TechBiz Global GmbH
Località Italia | IT
Contratto Full Time

Descrizione del lavoro:

Ultime informazioni sul lavoro da TechBiz Global GmbH per la posizione di Senior Formal Verification Engineer - Vector Unit. If the Senior Formal Verification Engineer - Vector Unit vacante in Italia corrisponde al tuo profilo, invia il tuo CV aggiornato direttamente tramite il portale Jobkos.

Tieni presente che candidarsi per un lavoro richiede tempo, poiché i candidati devono soddisfare determinati requisiti aziendali. Speriamo che l'opportunità presso TechBiz Global GmbH per la posizione di Senior Formal Verification Engineer - Vector Unit sia in linea con le tue qualifiche.

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this Posizione, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.


Posizione is on-site from Barcelona!
Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

  • End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
  • Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
  • Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
  • RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
  • Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

  • Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
  • SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Info sul lavoro:

  • Azienda: TechBiz Global GmbH
  • Posizione: Senior Formal Verification Engineer - Vector Unit
  • Luogo di lavoro: Italia
  • Paese: IT

Come inviare la candidatura:

Dopo aver letto e compreso i criteri e i requisiti minimi indicati nelle informazioni sull'offerta Senior Formal Verification Engineer - Vector Unit at the office Italia sopra indicato, prepara immediatamente i documenti necessari come lettera di presentazione, CV, copia del titolo di studio e altri allegati. Invia tramite il link Pagina Successiva qui sotto.

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